High speed arithmetic computation is a critical design factor in many information handling systems such as computers, signal processors and process controllers. These systems increasingly rely on large scale integrated circuits employing highly parallel designs to provide high speed calculations. While devices that perform multiplication using parallel techniques are widely available, devices for performing the division and square root functions are generally serial in nature and therefore operate at slower speeds.
Calculating division and square roots, unlike addition, subtraction or multiplication, is an iterative process. An apparatus or circuit for performing the division or square root function will take a number of steps or clock cycles to arrive at a quotient or root value. The execution time and accuracy of an information handling system can be greatly affected by the technique employed for performing the division and square root functions. One known technique involves using a convergence algorithm.
In division, a convergence algorithm treats the dividend and divisor as a fraction. If repeated multiplication of the divisor (i.e. the denominator of the fraction) by some function of the divisor forces the denominator to one in the limit, then repeated multiplication of the dividend by the same function will force it to the quotient in the limit. In a square root calculation, the number for which the square root is to be determined is treated as a fraction where the number is the same for the numerator and denominator. Repeated multiplication of the fraction by some function forces the denominator to one and the numerator to the square root in the limit.
Division and square roots, in information handling systems, can be performed by employing high speed multipliers in conjunction with other circuitry operating in accord with a convergence algorithm. A typical convergence algorithm requires repeated multiplication steps to arrive at a result. As a consequence, prior art high speed multipliers require at least three clock cycles for each duration of the convergence algorithm. Hence, division and square root calculations require a substantial amount of time relative to other calculations.
Because of the desire for ever faster information handling systems, a need has arisen to provide a processor which is capable of high speed division and square root calculations.